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Cause my PAPI told me to To give competitors a fighting chance To show my boss how great my branch predictor is (ie., get a raise) To improve the performance of current and future systems4  9$6I/=How much Performance would you give up for PMU Functionality?*> Transistors may be  free but& Wires are not! Design time costs Validation costs Documentation costs Time to Market costs The answer is not 0% PMU proven to improve performance But it s not 10% either!tZ[ZZ"ZZ["70What to Architect in the PMU? Machine Architecture is a contract between hardware and software Architect too much& Lowers performance through design constraints Events don t map well to hardware Architect too little& Jeopardizes Software Investment Discourages Software SupportTWZPZZ=ZWP=1Itanium Architecture: PMU& Architected Access & Management of PMU Resources PMD registers for Data, PMC registers to control PMU Counter Overflow Behavior and Interrupt Handling Only a few basic counter events Implementation Dependent Number of counters, width of counters Non-counter performance monitors Events: Encourage use of CPU-specific tables Itanium architecture protects OS and Tool infrastructure while promoting performance and full visibility Z%Z5ZQZZtZiZ %5Qt  i2VPerformance Events  Let me count the ways& ,,bWhich events are important? How will the events be used? Do you really care about a cache miss if it doesn t cause any stalls? Mapping an event to signals Needed signal may not be available On critical path, lack of wires, no signal Combining signals is problematic Distance between signals, timing, logicc#+!(c#+! (@ Itanium 2 Processor PMU Events*  4#Where are the Performance Problems?$Counters only give type of problem and magnitude of the problem Use filters on counters (hunt & peck) Itanium architecture currently includes: Opcode Filters Privilege Level Filters Instruction Address Range Filters Data Address Range Filters>ZdZm "d^A!+A Better Way to Locate Performance Problems,,Event Address Registers (EARs) Logs information about a single cache miss The logs are sampled by software Creates a statistical profile of cache misses Branch Trace Buffer (BTB) Logs information about consecutive branches Logs also sampled by softwareTZzZZJZzJB"Lend Me an EARInstruction & Data EARs Log Instruction Address of Miss Data EAR also logs Data Address of Miss Log Latency of Miss Filter by latency bin Have an associated counter event Can also log TLB misses And where TLB miss was resolved Have proven to be extremely useful (c # (c   The D-EAR Shadow EffectC#The D-EAR Shadow EffectE$jThe Itanium 2 Processor s Branch Trace Buffer (BTB)*6  *)An eight entry Circular Buffer Each entry contains either: Address & Prediction Data of a branch, or Address of a branch target Uses of the BTB Mis-predicted branch profiler An efficient Instruction Address Profiler Path Profiler Cool use: in conjunction with EARs Path leading up to sampled miss!;ZEZZVZ#Z!Z;EV#!  ,q"F%pThe Itanium 2 processor s PMU Helps Improve Performance*9  -G& ConclusionsWalking a micron in HW design shoes Balancing PMU functionality & overall performance We need to move beyond counters! Itanium 2 processors provide EARs and BTBs What s next? The Itanium 2 processor s PMU has much to offer Customers are making good use of it Would like to see more use  how do we do it? Discussion What is the long-term vision for the PMU? What can the PMU provide to improve current and future systems Did anything  stick or resonate? $Z2Z!Z9Z0ZRZ ZZ$2!  10R  ,'H',For More Information& .!http://developer.intel.com/design/itanium/documentation.htm Manuals Intel Itanium Architecture Software Developer's Manuals Volume 1: Application Architecture Part II: Optimization Guide Intel Itanium Architecture Software Developer's Manuals Volume 2: System Architecture Chapter 7: Debugging and Performance Monitoring Chapter 12: Performance Monitoring Support Intel Itanium 2 Processor Reference Manual for Software Development and Optimization Chapter 10: Performance Monitoring Chapter 11: Performance Monitor Events N";   J4Z"UcTP 0; 0J 0 0~/8Dr   0` f3|` 3f3` ___>?" dd@ 33?" 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Fonts UsedDesign Template Slide Titles8 8@ _PID_HLINKSA<http://developer.intel.com/design/itanium/documentation.htmBhttp://developer.intel.com/design/itanium/manuals/iiasdmanual.htm applicationBhttp://developer.intel.com/design/itanium/manuals/iiasdmanual.htmsystem>http://developer.intel.com/design/itanium2/manuals/251110.htmPowerPoint Document(,NDocumentSummaryInformation8