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$ %4"$@NZAU랩lc b$j^SZ| n/Z b$>jӈ'3Fa"8$$$R$%X.2[rQc $0e0e     Ad @ A1 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||@83ʚ;ʚ;g4YdYd| 0ppp@ <4dddd w 0Tu 80___PPT10 ?% Pentium is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countriesO /Performance Monitoring on Pentium 4* Processor,0$    7Nidhi nidhi.nidhi@intel.com IA 32 Performance Architect88Outline Pentium 4* Processor Performance Monitoring features Implementation How Intel uses Performance Monitors Limitations Open issues XG% Feature Overview Counters 18 40-bit programmable counters Events 45 events in various parts of the machine Counter increment control qualification by current privilege level (O/S, USER) qualification by hardware thread id edge detection threshold comparison interrupt on counter overflow Interface ( x86 instructions to set/read counters) WRMSR (write machine status register) RDMSR (read machine status register) RDPMC (read performance monitoring counter) RDTSC (read time-stamp counter) ZZ3ZZZ *3Features Overview, cont. V Cascading Second counter begins counting when first counter overflows For instance, to measure cycles elapsed after the first counter overflowed. Tagging Used to get non-speculative event counts Tags micro-ops when they incur an event Counts tagged micro-ops at retirement Three tagging mechanisms: front-end, execution, and replay          Precise Event Based Sampling Mechanism User allocates a PEBS buffer in memory User programs a counter to tag micro-ops and count them as they retire When the counter overflows, the Pentium 4 Processor  s retirement logic forces a microcode assist just before the next tagged micro-op Microcode assist copies the program counter and GPRs into the PEBS buffer in memory Advantages Precise: taken at instruction which had an event Enables creation of data profiles and locate cache lookup patterns and data relocation opportunities  UKUU UUUU K ,1 Implementation Overview   $How Intel Uses Performance Monitors&%   Intel uses Performance Monitoring for: Performance Analysis Compiler optimizations System level optimizations Performance and functional debug Many tools built for analyzing and collecting Performance monitoring counters Interval Sampler Profiler (i N(iN   Performance Analysis  *Interval sampler Gives the characteristics of the system VTune"! Performance Analyzer Event Profiler Gives the distribution of events for the system over the whole application run Available at: http://www.intel.com/software/products/vtune/ Interval Sampler points out which events to look for, VTune"! event profiles then help find the function, basic block or the IPs that have the performance problem. U(UUUUUUU(m-  Limitations  wNot all counters can count all events. With hyperthreading, the counters may get divided among the logical processors. "xw Open Questions  HCentralized Vs. Distributed? Distributed is simpler but less flexible Add new events? New usage models Multicore / Multithread scenarios Feedback is welcome! J )5 )5Backup *Hyper threading And Performance Monitoring++Changes Performance Monitoring events/counters had to be made thread aware. Used for Debug Performance Monitoring was used to detect Multithread functional/ fairness issues. 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V Cascading Second counter begins counting when first counter overflows For instance, to measure cycles elapsed after the first counter overflowed. Tagging Used to get non-speculative event counts Tags micro-ops when they incur an event Counts tagged micro-ops at retirement Three tagging mechanisms: front-end, execution, and replay          Precise Event Based Sampling Mechanism User allocates a PEBS buffer in memory User programs a counter to tag micro-ops and count them as they retire When the counter overflows, the Pentium 4 Processor  s retirement logic forces a microcode assist just before the next tagged micro-op Microcode assist copies the program counter and GPRs into the PEBS buffer in memory Advantages Precise: taken at instruction which had an event Enables creation of data profiles and locate cache lookup patterns and data relocation opportunities  UKUU UUUU K ,1 Implementation Overview   $How Intel Uses Performance Monitors&%   Intel uses Performance Monitoring for: Performance Analysis Compiler optimizations System level optimizations Performance and functional debug Many tools built for analyzing and collecting Performance monitoring counters Interval Sampler Profiler (i N(iN   Performance Analysis  *Interval sampler Gives the characteristics of the system VTune"! Performance Analyzer Event Profiler Gives the distribution of events for the system over the whole application run Available at: http://www.intel.com/software/products/vtune/ Interval Sampler points out which events to look for, VTune"! event profiles then help find t  !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~Root EntrydO)l5@Pictures#Current UserkSummaryInformation(H4Ut      !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqruvwxyz{|}~ ngsRomanTT4uܖ 0ܖ B0.  @n?" dd@  @@`` LD5B   # $ %4"$@NZAU랩lc b$j^SZ| n/Z b$>jӈ'3Fa"8$$$R$%X.2[rQc $0e0e     Ad @ A1 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||@83ʚ;ʚ;g4YdYd| 0ppp@ <4dddd w 0Tu 80___PPT10 ?% Pentium is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countriesO /Performance Monitoring on Pentium 4* Processor,0$    7Nidhi nidhi.nidhi@intel.com IA 32 Performance Architect88Outline Pentium 4* Processor Performance Monitoring features Implementation How Intel uses Performance Monitors Limitations Open issues XG% Feature Overview Counters 18 40-bit programmable counters Events 45 events in various parts of the machine Counter increment control qualification by current privilege level (O/S, USER) qualification by hardware thread id edge detection threshold comparison interrupt on counter overflow Interface ( x86 instructions to set/read counters) WRMSR (write machine status register) RDMSR (read machine status register) RDPMC (read performance monitoring counter) RDTSC (read time-stamp counter) ZZ3ZZZ *3Features Overview, cont. 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Tagging Used to get non-speculative event counts Tags micro-ops when they incur an event Counts tagged micro-ops at retirement Three tagging mechanisms: front-end, execution, and replay          Precise Event Based Sampling Mechanism User allocates a PEBS buffer in memory User programs a counter to tag micro-ops and count them as they retire When the counter overflows, the Pentium 4 Processor  s retirement logic forces a microcode assist just before the next tagged micro-op Microcode assist copies the program counter and GPRs into the PEBS buffer in memory Advantages Precise: taken at instruction which had an event Enables creation of data profiles and locate cache lookup patterns and data relocation opportunities  UKUU UUUU K ,1 Implementation Overview   $How Intel Uses Performance Monitors&%   Intel uses Performance Monitoring for: Performance Analysis Compiler optimizations System level optimizations Performance and functional debug Many tools built for analyzing and collecting Performance monitoring counters Interval Sampler Profiler (i N(iN   Performance Analysis  *Interval sampler Gives the characteristics of the system VTune"! Performance Analyzer Event Profiler Gives the distribution of events for the system over the whole application run Available at: http://www.intel.com/software/products/vtune/ Interval Sampler points out which events to look for, VTune"! event profiles then help find the function, basic block or the IPs that have the performance problem. U(UUUUUUU(m-  Limitations  wNot all counters can count all events. With hyperthreading, the counters may get divided among the logical processors. "xw Open Questions  HCentralized Vs. Distributed? Distributed is simpler but less flexible Add new events? New usage models Multicore / Multithread scenarios Feedback is welcome! J )5 )5Backup *Hyper threading And Performance Monitoring++Changes Performance Monitoring events/counters had to be made thread aware. Used for Debug Performance Monitoring was used to detect Multithread functional/ fairness issues. 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FTFT/rܐ Fwb&(     Visio Visio.Drawing.60.Microsoft Visio Drawing/ 0DArialngsRomanTT4uܖ 0ܖDTimes New RomanTT4uܖ 0ܖ DWingdingsRomanTT4uܖ 0ܖ B0.  @n?" dd@  @@`` LD5B   # $ %4"$@NZAU랩lc b$j^SZ| n/Z b$>jӈ'3Fa"8$$$R$%X.2[rQc $0e0e     Ad @ A1 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||@83ʚ;ʚ;g4YdYd| 0ppp@ <4dddd w 0Tu 80___PPT10 ?% Pentium is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countriesO /Performance Monitoring on Pentium 4* Processor,0$    7Nidhi nidhi.nidhi@intel.com IA 32 Performance Architect88Outline Pentium 4* Processor Performance Monitoring features Implementation How Intel uses Performance Monitors Limitations Open issues XG% Feature Overview Counters 18 40-bit programmable counters Events 45 events in various parts of the machine Counter increment control qualification by current privilege level (O/S, USER) qualification by hardware thread id edge detection threshold comparison interrupt on counter overflow Interface ( x86 instructions to set/read counters) WRMSR (write machine status register) RDMSR (read machine status register) RDPMC (read performance monitoring counter) RDTSC (read time-stamp counter) ZZ3ZZZ *3Features Overview, cont. V Cascading Second counter begins counting when first counter overflows For instance, to measure cycles elapsed after the first counter overflowed. Tagging Used to get non-speculative event counts Tags micro-ops when they incur an event Counts tagged micro-ops at retirement Three tagging mechanisms: front-end, execution, and replay          Precise Event Based Sampling Mechanism User allocates a PEBS buffer in memory User programs a counter to tag micro-ops and count them as they retire When the counter overflows, the Pentium 4 Processor  s retirement logic forces a microcode assist just before the next tagged micro-op Microcode assist copies the program counter and GPRs into the PEBS buffer in memory Advantages Precise: taken at instruction which had an event Enables creation of data profiles and locate cache lookup patterns and data relocation opportunities  UKUU UUUU K ,1 Implementation Overview   $How Intel Uses Performance Monitors&%   Intel uses Performance Monitoring for: Performance Analysis Compiler optimizations System level optimizations Performance and functional debug Many tools built for analyzing and collecting Performance monitoring counters Interval Sampler Profiler (i N(iN   Performance Analysis  *Interval sampler Gives the characteristics of the system VTune"! Performance Analyzer Event Profiler Gives the distribution of events for the system over the whole application run Available at: http://www.intel.com/software/products/vtune/ Interval Sampler points out which events to look for, VTune"! event profiles then help find the function, basic block or the IPs that have the performance problem. U(UUUUUUU(m-  Limitations  wNot all counters can count all events. With hyperthreading, the counters may get divided among the logical processors. "xw Open Questions  HCentralized Vs. Distributed? Distributed is simpler but less flexible Add new events? New usage models Multicore / Multithread scenarios Feedback is welcome! J )5 )5Backup *Hyper threading And Performance Monitoring++Changes Performance Monitoring events/counters had to be made thread aware. Used for Debug Performance Monitoring was used to detect Multithread functional/ fairness issues. FTFT/rz Vwr&(     Visio Visio.Drawing.60.Microsoft Visio Drawing/ 0DArialngsRomanllv 0DTimes New Romanllv 0 DWingdingsRomanllv 0 B0.  @n?" dd@  @@`` LD5B   # $ %4"$@NZAU랩lc b$j^SZ| n/Z b$>jӈ'3Fa"8$$$R$%X.2[rQc $0e0e     Ad @ A1 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||@83ʚ;ʚ;g4kdkdTt  0|ppp@ <4dddd8w 0lu 80___PPT10 ?% Pentium is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countriesO /Performance Monitoring on Pentium 4* Processor,0$    7Nidhi nidhi.nidhi@intel.com IA 32 Performance Architect88Outline Pentium 4* Processor Performance Monitoring features Implementation How Intel uses Performance Monitors Limitations Open issues XG% Feature Overview Counters 18 40-bit programmable counters Events 45 events in various parts of the machine Counter increment control qualification by current privilege level (O/S, USER) qualification by hardware thread id edge detection threshold comparison interrupt on counter overflow Interface ( x86 instructions to set/read counters) WRMSR (write machine status register) RDMSR (read machine status register) RDPMC (read performance monitoring counter) RDTSC (read time-stamp counter) ZZ3ZZZ *3Features Overview, cont. V Cascading Second counter begins counting when first counter overflows For instance, to measure cycles elapsed after the first counter overflowed. Tagging Used to get non-speculative event counts Tags micro-ops when they incur an event Counts tagged micro-ops at retirement Three tagging mechanisms: front-end, execution, and replay          Precise Event Based Sampling Mechanism User allocates a PEBS buffer in memory User programs a counter to tag micro-ops and count them as they retire When the counter overflows, the Pentium 4 Processor  s retirement logic forces a microcode assist just before the next tagged micro-op Microcode assist copies the program counter and GPRs into the PEBS buffer in memory Advantages Precise: taken at instruction which had an event Enables creation of data address profiles and locate cache lookup patterns and data relocation opportunities  UKUU UUUU K ,1 Implementation Overview   $How Intel Uses Performance Monitors&%   Intel uses Performance Monitoring for: Performance Analysis Compiler optimizations System level optimizations Performance and functional debug Many tools built for analyzing and collecting Performance monitoring counters Interval Sampler Profiler (i N(iN   Performance Analysis  *Interval sampler Gives the characteristics of the system VTune"! Performance Analyzer Event Profiler Gives the distribution of events for the system over the whole application run Available at: http://www.intel.com/software/products/vtune/ Interval Sampler points out which events to look for, VTune"! event profiles then help find the function, basic block or the IPs that have the performance problem. U(UUUUUUU(m-  Limitations  wNot all counters can count all events. With hyperthreading, the counters may get divided among the logical processors. "xw Open Questions  HCentralized Vs. Distributed? Distributed is simpler but less flexible Add new events? New usage models Multicore / Multithread scenarios Feedback is welcome! J )5 )5Backup *Hyper threading And Performance Monitoring++Changes Performance Monitoring events/counters had to be made thread aware. Used for Debug Performance Monitoring was used to detect Multithread functional/ fairness issues. FTFT/0  0 `0(  x  c $|A   x  c $}0A  H  0޽h ? 3380___PPT10.eH[rwB$(     Visio Visio.Drawing.60.Microsoft Visio Drawing/ 0DArialngsRomanTTyܖ 0ܖDTimes New RomanTTyܖ 0ܖ DWingdingsRomanTTyܖ 0ܖ B0.  @n?" dd@  @@`` LD5<   # $ 4"$@NZAU랩lc b$j^SZ| n/Z b$>jӈ'3Fa"8$$$R$%X.2[rQc $0e0e     Ad @ A1 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||@83ʚ;ʚ;g4kdkd 0|ppp@ <4dddd w 0Txy 80___PPT10 ?% Pentium is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countriesO i/Performance Monitoring on Pentium 4* Processor,0$    7Nidhi nidhi.nidhi@intel.com IA 32 Performance Architect88Outline Pentium 4* Processor Performance Monitoring features Implementation How Intel uses Performance Monitors Limitations Open issues XG% Feature Overview Counters 18 40-bit programmable counters Events 45 events in various parts of the machine Counter increment control qualification by current privilege level (O/S, USER) qualification by hardware thread id edge detection threshold comparison interrupt on counter overflow Interface ( x86 instructions to set/read counters) WRMSR (write machine status register) RDMSR (read machine status register) RDPMC (read performance monitoring counter) RDTSC (read time-stamp counter) ZZ3ZZZ *3Features Overview, cont. V Cascading Second counter begins counting when first counter overflows For instance, to measure cycles elapsed after the first counter overflowed. Tagging Used to get non-speculative event counts Tags micro-ops when they incur an event Counts tagged micro-ops at retirement Three tagging mechanisms: front-end, execution, and replay          Precise Event Based Sampling Mechanism User allocates a PEBS buffer in memory User programs a counter to tag micro-ops and count them as they retire When the counter overflows, the Pentium 4 Processor  s retirement logic forces a microcode assist just before the next tagged micro-op Microcode assist copies the program counter and GPRs into the PEBS buffer in memory Advantages Precise: taken at instruction which had an event Enables creation of data address profiles and locate cache lookup patterns and data relocation opportunities  UKUU UUUU K ,1 Implementation Overview   $How Intel Uses Performance Monitors&%   Intel uses Performance Monitoring for: Performance Analysis Compiler optimizations System level optimizations Performance and functional debug Many tools built for analyzing and collecting Performance monitoring counters Interval Sampler Profiler (i N(iN   Performance Analysis  *Interval sampler Gives the characteristics of the system VTune"! Performance Analyzer Event Profiler Gives the distribution of events for the system over the whole application run Available at: http://www.intel.com/software/products/vtune/ Interval Sampler points out which events to look for, VTune"! event profiles then help find the function, basic block or the IPs that have the performance problem. U(UUUUUUU(m-  Limitations  wNot all counters can count all events. With hyperthreading, the counters may get divided among the logical processors. "xw Open Questions  HCentralized Vs. Distributed? Distributed is simpler but less flexible Add new events? New usage models Multicore / Multithread scenarios Feedback is welcome! J )5 )5/r P+w  4* ProcessorOutlineFeature OverviewFeatures Overview, cont.Precise Event Based SamplingImplementation Overview%How Intel Uses Performance MonitorsPerformance Analysis Limitations Open Questions  Fonts UsedDesign TemplateEmbedded OLE Servers Slide Titles 41_`+4HiPersoft Rice UniversityHiPersoft Rice University  $, PowerPoint Document(+DocumentSummaryInformation8՜.+,D՜.+,x4   ( 0 On-screen Show(Windows XP build Engineering Computing+b  ArialTimes New Roman WingdingsDPG_circuitry_2004Microsoft Visio Drawing0Performance Monitoring on Pentium