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Jack Dongarra, Shirley Moore, Phil Mucci, Keith Seymour, and Haihang You (2004)
Accurate Cache and TLB Characterization Using hardware Counters
In: Proceedings of the International Conference on Computational Science (ICCS) 2004, Krakow, Poland, 233 Spring Street, New York, NY 10013, Springer.
We have developed a set of microbenchmakrs for accurately determining the structural characteristics of data cache memories and TLBs. These characteristics include cache size, cache line size, cache associativity, memory page size, number of data TLB entries, and data TLB associativity. Unlike previous microbenchmarks that used time- based measurements, our microbenchmarks use hardware event counts to more accurately and quickly determine these characteristics while requiring fewer limiting assumptions.
